View LH77790B_8997359.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LH77790B embedded microcontroller thermal & electrical specification version 1.0 ?
sharp reserves the right to make changes in specifications described herein at any time and with- out notice in order to improve design or reliability. sharp does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied. sharp assumes no responsibility for damage caused by misuse or improper use of devices. life support policy sharp components should not be used in medical devices with life support functions, safety equip- ment (or similar applications where component failure would result in loss of life or physical harm), aerospace equipment, telecommunication equipment (trunk lines) or nuclear power control equip- ment. contact a sharp representative or sales office before using sharp devices for any applica- tions other than those recommended by sharp. limited warranty sharp warrants to its customer that the products will be free from defects in material and workman- ship under normal use and service for a period of one year from the date of invoice. customer?s exclusive remedy for breach of this warranty is that sharp will either (i) repair or replace, at its option, any product which fails during the warranty period because of such defect (if customer promptly reported the failure to sharp in writing) or, (ii) if sharp is unable to repair or replace, refund the purchase price of the product upon its return to sharp. this warranty does not apply to any product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than sharp. the warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. all express and implied warranties, including the warran- ties of merchantability, fitness for use and fitness for a particular pur- pose, are specifically excluded. in no event will sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage. the above warranty is also extended to customers of sharp authorized distributors with the follow- ing exception: reports of failures of products during the warranty period and return of products that were purchased from an authorized distributor must be made through the distributor. in case sharp is unable to repair or replace such products, refunds will be issued to the distributor in the amount of distributor cost. trademark advanced risc machines, united kingdom. LH77790B embedded microcontroller preliminary user?s guide version 1.0 ? 1999 copyright sharp microelectronics of the americas. printed and bound in usa. reference no. sma99104
thermal & electrical specification 1 thermal & electrical specification overview portable devices are becoming more and more prevalent in our daily life. they are used as personal information managers, communication devices, digital cameras, handheld games, bar-code scanners, medical equipment, electronic instrumentation, and navigation systems. there are significant design challenges for portable devices. low cost is a top priority for high volume products. low power is a must for long battery life. high perfor- mance is critical for computationally-intensive applications such as pdas, gps, and 2-d scanners. communication capabilities and effective user interface are integral parts of any portable device. last, but not least, superior product development support tools are crucial to reducing time-to-market. the sytem on chip team at sharp has designed the LH77790B embedded microcon- troller (a.k.a. 790b) to meet the above challenges in portable design. the LH77790B, pow- ered by an arm7di?, is a complete system on chip with a high level of integration to satisfy a wide range of customer requirements and expectations. the 790b combines a 32-bit arm7di risc engine, a number of essential peripherals (uarts, counter/timers, pios, pwms, etc...), lcd controller, cache, and on-chip sram. this high level of integration lowers overall system cost, reduces development cycle time and accelerates product introduction. the 790b?s fully static design, power management unit, dual voltage operation (3.3 v/5 v), fast interrupt response time, on-chip cache and sram, powerful instruction set, and very low power risc core provide high performance at low current draw. the on-chip lcd controller, uarts, irda/dask, and the programma- ble peripheral interface (ppi) are well suited for wireless, cable, and visual communication requirements. other features like, watchdog timer, programmable memory interface, on- chip sram/dram controllers and debug support provides a high level of flexibility. please check our website at www.sharpsma.com or with your local sharp sales office for the latest thermal and electrical specifications and/or errata sheets. these documents will contain the latest parameters for the LH77790B.
LH77790B 2 thermal & electrical specification features highly integrated single chip 32-bit arm7di risc core ? built-in debug and ice support ? fast interrupt response ? powerful instruction set 26-bit external address bus ? 512mb addressable space 16-bit external data bus 2kb data/instruction cache ? 4 way set associative ? write back policy ? flexible modes of operation 2kb static ram ? expandable to 4kb without cache low power high performance programmable clock and power management programmable monochrome lcd controller ? 1024 (v) 2048 (h) ? four gray shades ? frame buffer in main memory on-chip interrupt controller ? six external interrupts ? seven internal interrupts ? arm7di wake-up three uarts - 16c450-class ? full modem support on uart0 ? partial modem support on uart1 ? irda-1.0/dask support on uart2 irda/dask ir interface ? irda-1.0 (2.4 kbps to 115.2 kbps) ? dask (2.4 kbps to 57.6 kbps) three pulse width modulator channels ? pwm0 and pwm1 have 8-bit resolution ? pwm2 has 16-bit resolution
LH77790B thermal & electrical specification 3 flexible memory interface ? six multiplexeled chip enables/cas pins ? two ras pins ? fully programmable ? six sram banks (64mb each) ? two dram banks (128mb each) ? access privileges (system/user) on-chip dram controller ? fast page mode ? normal mode ? cas before ras refresh programmable peripheral interface (ppi) ? 24 programmable i/o signals ? three modes of operation three 16-bit counter/timer channels ? six modes of operation ? binary or bcd counting hardware watchdog timer ? eight time-out intervals ? protection mechanism ? three time-out actions little endian jtag interface dual supply voltage ? 5 v ttl - 25 mhz ? 3.3 v lvttl - 16.7 mhz development environment the 790b evaluation board (part number lu7790ah2a) and the arm software develop- ment toolkit (part number lu7v211h1) give users full access to the power and features of the 790b and provide a complete integrated environment for development. users will be able to develop, benchmark, and profile both hardware and software easily and quickly.
LH77790B 4 thermal & electrical specification block diagram figure 1. LH77790B block diagram clock/power management int/reset controller lcd controller 82c54 counter/ timers bus controller external memory interface pwm 3 channels clock(s) 24 bits ch 0 ch 0/ch 1 ch 1 ch 2 ch 2 arm7di cpu and cache arm-8 jtag interrupts reset lcd display 82c55 programmable peripheral interface watch dog timer 16c450 uarts 32-bit internal bus irda/ dask 2k bytes scratch pad sram arm7di tap controller
LH77790B thermal & electrical specification 5 pin description table 1. pin descriptions pins name direction description external bus interface 36 - 31, 28 - 21, 18 - 11, 8 - 5 a[25:0] o external address bus. the 790b will provide a 26-bit address to exter- nal memories and peripherals. 60 - 55, 52 - 47, 42 - 41, 38 - 37 d[15:0] i/o external 16-bit data bus. 72 oe o output enable for external memory and peripherals. oe allows external memory and peripherals to drive the data bus and is asserted low dur- ing a read access and high during a write access. 71 we o write enable for external memory and peripherals. during a write access, this pin is driven low. during a read access, this pin is driven high. 70 - 65 ce [5:0]/ cas [5:0] o these pins provide the chip enable/column address select signals al- lowing direct connection to standard external memory/peripheral devic- es. the pins act as cas when interfacing to drams and as ce otherwise. they are fully programmable by the system designer and can support byte enables. 62 - 61 ras [1:0] o row address select pins for dram bank 0 and bank 1. 74 wait i external memory wait. allows the use of slow memories. the 790b generates external wait cycles (ewc) in response to activating wait . wait is sampled on the high to low transition on xclk. to add one ewc, wait must be active prior to sampling in the last cycle (beginning of the last cycle) of a memory transfer. if wait continues to be active (when sampled) in subsequent cycles, more ewc will be added. once wait is deactivated, the 790b will complete the memory transfer. 73 bw o byte wide access. bw is low when the arm7di executes a store/ load byte instruction. bw is high when the arm7di core executes a store/load word instruction or an instruction fetch. bw does not depend on the bus size of the external memory/peripheral device. bw is valid during an external memory access. it can be used by an external ad- dress decoder to generate extra chip/byte enables. bw is a don't care during dram refresh. 169 bb i byte boot selects between x8 or x16 for the boot memory. the 790b samples and captures the state of bb on the rising edge of reseti allowing bb to change state after reset. if bb is low the 790b will boot from a x8 memory. if bb is high, the 790b will boot from a x16 mem- ory. this pin is normally tied low for x8 boot memory or high for x16 boot memory. counters/timers interface 123, 121, 117 ctgate[2:0] i counter/timer control gate input signals. 124, 122, 118 ctout[2:0] o counter/timer output signals. interrupt interface 107 - 102 int[5:0] i external interrupt input signals.
LH77790B 6 thermal & electrical specification lcd controller interface 91 cp2 o shift/pixel clock. 92 cp1 o line pulse/hsync. 93 mclk o ac modulation signal. 94 s o frame pulse/vsync. 95 lcdcntl o lcd control signal. 84 - 77 vd[7:0] o video data. programmable peripheral interface 139 - 135, 128 - 126 149 - 145, 142 - 140 159 - 155, 152 - 150 pa[7:0] pb[7:0] pc[7:0] i/o parallel ports a, b, and c signals. signals have programmable access and can function as input, output or controls (port c only). pb[7:2] and pc[2:0] are multiplexed with uarts modem signals. pwm interface 98 - 96 pwm[2:0] o pulse width modulator output signals. uarts interface 114, 112, 108 rxd[2:0] i uart serial data input signals. rxd2 also doubles as the digital input for the ir interface. 115, 113, 111 txd[2:0] o uart serial data output signals. txd2 also doubles as the digital output for the ir interface. 150, 151 rts [1:0] o request to send for uart0 and uart1. multiplexed with pc0 and pc1 respectively. 145, 146 cts [1:0] i clear to send for uart0 and uart1. multiplexed with pb3 and pb4 respectively. 142, 147 ri [1:0] i ring indicator for uart0 and uart1. multiplexed with pb2 and pb5 respectively. 152 dtr0 o data terminal ready for uart0 only. multiplexed with pc2. 149 dsr0 i data set ready for uart0 only. multiplexed with pb7. 148 dcd0 i data carrier detect for uart0 only. multiplexed with pb6. reset and external clocks 101 reseti** i chip and jtag tap controller reset input. reseti has a built-in glitch detector. reseto will be driven low after a valid reset is detected for as long as reseti is driven low. jtag reset, trst, is internally con- nected to reseti . 119 reseto o chip reset output. it will be driven low during: 1. chip reset 2. wdt timeout reset 3. software controlled reset 3 xclk i the 790b external clock input pin. duty cycle is 50%. 162 xclkdis o xclkdis is an active high output pin that can be used to disable ex- ternal clock circuitry and will result in reducing current consumption to micro-amperes. xclkdis is high in sleep and stop modes. connect- ing this pin to the external clock circuitry, allows the 790b to go into stop mode by disabling the external clock. 116 uclk i uart/dask demodulator external clock input signal. duty cycle is 50%. 125 ctclk i counter/timer external clock input signal. duty cycle is 50%. table 1. pin descriptions pins name direction description
LH77790B thermal & electrical specification 7 note: *jtag reset, trst , is internally connected to reseti . ieee 1149.1 ? 1990 standard requires jtag inputs to be pulled up to a good logic level to achieve normal operations. jtag interface* 160 tck i jtag test/embeddedice ? clock input signal. must be pulled-up for normal operation (56 k ? is recommended for compatibility with arm ? s embeddedice) 161 tms i jtag test/embeddedice mode select input signal. must be pulled-up for normal operation (56 k ? is recommended for compatibility with arm ? s embeddedice) 165 tdi i jtag test/embeddedice data input signal. must be pulled-up for normal operation (56 k ? is recommended for compatibility with arm ? s embeddedice) 166 tdo o jtag test/embeddedice data output signal. reserved interface 170 adbe i reserved. must be tied high for normal operation. 167 test0 i reserved. must be tied low for normal operation. 168 test1 o reserved. no connect. 171 test2 i reserved. must be tied low for normal operation 172 test3 o reserved. no connect power signals 9, 19, 29, 39, 53, 63, 75, 85, 99, 109, 129, 143, 153, 163, 173 v cc i power. all LH77790B are 5 v/3.3 v. 4, 10, 20, 30, 40, 54, 64, 76, 86, 100, 110, 120, 130, 144, 154, 164, 174 v ss i ground. all ground pins must be used. no connect 1, 2, 43, 44, 45, 46, 87, 88, 89, 90, 131, 132, 133, 134, 175, 176 nc ? no connection. table 1. pin descriptions pins name direction description
LH77790B 8 thermal & electrical specification table 2. pinout pin signal pin signal pin signal pin signal 1nc45nc89nc133nc 2nc46nc90nc134nc 3 xclk 47 d4 91 cp2 135 pa3 4v ss 48 d5 92 cp1 136 pa4 5 a0 49 d6 93 mclk 137 pa5 6a1 50d7 94s 138pa6 7 a2 51 d8 95 lcdcntl 139 pa7 8 a3 52 d9 96 pwm0 140 pb0 9v cc 53 vcc 97 pwm1 141 pb1 10 v ss 54 vss 98 pwm2 142 pb2/ri1 11 a4 55 d10 99 v cc 143 v cc 12 a5 56 d11 100 v ss 144 v ss 13 a6 57 d12 101 reseti 145 pb3/cts1 14 a7 58 d13 102 int0 146 pb4/cts0 15 a8 59 d14 103 int1 147 pb5/ri0 16 a9 60 d15 104 int2 148 pb6/dcd0 17 a10 61 ras0 105 int3 149 pb7/dsr0 18 a11 62 ras1 106 int4 150 pc0/rts1 19 v cc 63 v cc 107 int5 151 pc1/rts0 20 v ss 64 v ss 108 rxd0 152 pc2/dtr0 21 a12 65 ce0 /cas0 109 v cc 153 v cc 22 a13 66 ce1 /cas1 110 v ss 154 v ss 23 a14 67 ce2 /cas2 111 txd0 155 pc3 24 a15 68 ce3 /cas3 112 rxd1 156 pc4 25 a16 69 ce4 /cas4 113 txd1 157 pc5 26 a17 70 ce5 /cas5 114 rxd2 158 pc6 27 a18 71 we 115 txd2 159 pc7 28 a19 72 oe 116 uclk 160 tck 29 v cc 73 bw 117 ctgate0 161 tms 30 v ss 74 wait 118 ctout0 162 xclkdis 31 a20 75 v cc 119 reseto 163 v cc 32 a21 76 v ss 120 v ss 164 v ss 33 a22 77 vd0 121 ctgate1 165 tdi 34 a23 78 vd1 122 ctout1 166 tdo 35 a24 79 vd2 123 ctgate2 167 test0 36 a25 80 vd3 124 ctout2 168 test1 37 d0 81 vd4 125 ctclk 169 bb 38 d1 82 vd5 126 pa0 170 adbe 39 v cc 83 vd6 127 pa1 171 test2 40 v ss 84 vd7 128 pa2 172 test3 41 d2 85 v cc 129 v cc 173 v cc 42 d3 86 v ss 130 v ss 174 v ss 43 nc 87 nc 131 nc 175 nc 44 nc 88 nc 132 nc 176 nc
LH77790B thermal & electrical specification 9 absolute maximum ratings note: these are stress ratings for transient conditions only. operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. recommended operating conditions note: unused input pins should be pulled low or high to their inactive state. note: unused input pins should be pulled low or high to their inactive state. table 3. absolute maximum ratings parameter symbol rating unit supply voltage v cc -0.3 to 6.0 v input voltage v in -0.3 to v cc + 0.3 v output voltage v out -0.3 to v cc + 0.3 v storage temperature t stg -40 to +125 c power dissipation (package limit) pd pkg 1w table 4. LH77790B (5 v operation) recommended operating conditions parameter symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 000v clock frequency f xclk 0 ? 25 mhz operating temperature t opr 0 ? 70 c table 5. LH77790B (3.3 v operation) recommended operating conditions parameter symbol min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v supply voltage v ss 000 v clock frequency f xclk 0 ? 16.7 mhz operating temperature t opr 0 ? 70 c
LH77790B 10 thermal & electrical specification dc specifications over recommended operating voltage and temperature conditions, unless otherwise specified. notes: 1. ttl 2. cmos 3. condition 1: cmos input levels (note 2), for recommended operating conditions see table 4. xclk frequency = 25 mhz (5 v) or 16 mhz (3.3 v) 4. condition 2: same as condition 1 with core and peripherals halted. dram refresh is active. 5. condition 3: same as condition 2 with dram refresh disabled. 6. condition 4: same as condition 3 with xclk stopped. table 6. LH77790B dc specifications parameter symbol voltage range test condition min. max. unit notes input low voltage v il 3.3 v/5 v 0 0.8 v 1 input high voltage v ih 3.3 v/5 v 2.0 v cc v1 input low voltage v il 3.3 v/5 v 0 0.2 v 2 input high voltage v ih 3.3 v/5 v v cc ? 0.2 v cc v2 output low voltage v ol 3.3 v i ol = 1 ma, v cc = 3 v ? 0.4 v 1 5 v i ol = 2 ma, v cc = 4.5 v ? 0.4 v 1 output high voltage v oh 3.3 v i oh = -1 ma, v cc = 3 v 2.4 ? v 1 5 v i oh = -2 ma, v cc = 4.5 v 2.4 ? v 1 output low voltage v ol 3.3 v i ol = 100 a, v cc = 3 v ? 0.2 v 2 5 v i ol = 200 a, v cc = 4.5 v ? 0.2 v 2 output high voltage v oh 3.3 v i oh = -100 a, v cc = 3 v v cc ? 0.2 ? v 2 5 v i oh = -200 a, v cc = 4.5 v v cc ? 0.2 ? v 2 input leakage current i li 3.3 v/5 v v in = 0 v to v ccmax -5 5 a high impedance (off-state) output leakage current i oz 3.3 v/5 v v in = 0 v to v ccmax -5 5 a operating current (active mode) i ccat 3.3 v ? 60 ma 3 5 v ? 115 ma 3 operating current (standby mode) i ccsb 3.3 v ? 2 ma 4 5 v ? 4 ma 4 operating current (sleep mode) i ccsl 3.3 v ? 1 ma 5 5 v ? 2 ma 5 operating current (stop mode) i ccst 3.3 v operating temperature 0c to 50c ?40a6 5 v ? 200 a 6
LH77790B thermal & electrical specification 11 ac test conditions note: 1. applies to LH77790B (3.3 v and 5.0 v ranges). 2. includes scope and jig capacitance. pin capacitance note: 1. applies to LH77790B (3.3 v and 5.0 v ranges). 2. measurement condition: all pins are set to 0 v except measured pin. ac specifications over recommended operating voltage, temperature and ac test conditions. external clocks table 7. ac test conditions 1 parameter rating unit note input pulse levels v ss to v cc v input rise and fall times 5 ns input and output timing reference levels 1.5 v output load 50 pf 2 table 8. pin capacitance 1 parameter symbol max. unit note input capacitance c in 10 pf 2 output capacitance c out 20 pf 2 i/o capacitance c io 20 pf 2 figure 2. system clock ac timing t xclkl t xclk t xclkh arm2-99
LH77790B 12 thermal & electrical specification note: * when uclk is used as a dask demodulator clock, use a 14.318 mhz oscillator (50% duty). figure 3. external counters/timers clocks ac timing figure 4. external uarts/dask clock ac timing table 9. external clocks ac specifications parameter description 3.3 v range 5.0 v range unit min. max. min. max. t xclk xclk (system clock) period 60 ? 40 ? ns t xclkh xclk high time 1/2 ? 1/2 ? t xclk t xclkl xclk low time 1/2 ? 1/2 ? t xclk t ctclk ctclk (counters/timers external clock) period 2 ? 2 ? t xclk t ctclkh ctclk high time 1 ? 1 ? t xclk t ctclkl ctclk low time 1 ? 1 ? t xclk t uclk * uclk (uarts/dask external clock) period 2 ? 2 ? t xclk t uclkh * uclk high time 1 ? 1 ? t xclk t uclkl * uclk low time 1 ? 1 ? t xclk t ctclk t ctclkl arm2-100 t ctclkh arm2-101 t uclkh t uclk t uclkl
LH77790B thermal & electrical specification 13 sram/dram interface figure 5. sram read access ac timing xclk cycle 1 * a25 - a0 ce oe we bw d15 - d0 wait cycle 2 ** cycle 3 valid valid valid valid valid t xah t xce t xa t ds t dh t xceh t xoe t xoeh t xbwh t xbw t wts 1 t wth 1 arm2-102 notes: 1. wait = 0 790b will extend the memory access by adding an extra wait cycle. wait = 1 790b will not extend the memory access. memory access will complete as shown. 2. * 790b inserts an address setup cycle at the beginning of every non-sequential access (cycle1). ** sequential accesses do not have an address setup cycle. memory access starts with cycle2. *** sequential accesses only. ***
LH77790B 14 thermal & electrical specification figure 6. sram write access ac timing cycle 1 * cycle 2 ** *** cycle 3 arm2-103 xclk a25 - a0 valid valid d15 - d0 ce we oe bw wait t xwe t xweh t dweh t aweh t xbw t xbwh t xceh t dceh t aceh t xdh t xce t xd t xa t xah valid valid valid t wts 1 t wth 1 notes: 1. wait = 0 790b will extend the memory access by adding an extra wait cycle. wait = 1 790b will not extend the memory access. memory access will complete as shown. 2. * 790b inserts an address setup cycle at the beginning of every non-sequential access (cycle1). ** sequential accesses do not have an address setup cycle. memory access starts with cycle2. *** sequential accesses only.
LH77790B thermal & electrical specification 15 figure 7. dram read access ac timing cycle 1 * cycle 2 ** cycle 3 arm2-104 cycle 4 t xah t ds t xras t asr t xcas t xoe t asc t xbwh t xa dram row column t dh t xrash t xcash t xoeh t xbw xclk a25 - a0 d15 - d0 ras cas oe we bw wait valid t wts 1 t wth 1 notes: 1. wait = 0 790b will extend the memory access by adding an extra wait cycle. wait = 1 790b will not extend the memory access. memory access will complete as shown. 2. * 790b inserts an address setup cycle at the beginning of every non-sequential access (cycle1). ** sequential accesses do not have an address setup cycle. memory access starts with cycle2.
LH77790B 16 thermal & electrical specification figure 8. dram write access timing cycle 1 * cycle 2 ** cycle 3 arm2-105 cycle 4 t xah t xras t xcas t xwe t xbwh t xa dram row column t xdh t xrash t xcash t xweh t xbw xclk a25 - a0 d15 - d0 ras cas oe we bw wait t xd t asr t dsc t asc valid valid t wts 1 t wth 1 notes: 1. wait = 0 790b will extend the memory access by adding an extra wait cycle. wait = 1 790b will not extend the memory access. memory access will complete as shown. 2. * 790b inserts an address setup cycle at the beginning of every non-sequential access (cycle1). ** sequential accesses do not have an address setup cycle. memory access starts with cycle2. *** only for burst cas cycles in page mode (not shown). ***
LH77790B thermal & electrical specification 17 notes: 1. measures hold time on data bus until data changes. the change could either be a state change or high impedance change. 2. this parameter is the setup time when both data and cas become valid in the same cycle (burst cas cycles in page mode). 3. minimum data hold time with respect to ce , oe , and address invalid is 0 ns (sram). 4. minimum data hold time with respect to cas and oe invalid is 0 ns (dram). table 10. sram/dram ac specifications parameter description 3.3 v range 5.0 v range unit note min. max. min. max. t xa xclk to address valid ? 41 ? 33 ns t xah address hold relative to xclk 4 ? 4 ? ns t xce xclk to ce active ? 41 ? 27 ns t xceh ce hold relative to xclk 4 ? 4 ? ns t xwe (sram) xclk to we active (sram) ? 35 ? 30 ns t xwe (dram) xclk to we active (dram) ? 40 ? 35 ns t xweh we hold relative to xclk 4 ? 4 ? ns t wts wait setup relative to xclk 10 ? 10 ? ns t wth wait hold relative to xclk 6 ? 6 ? -ns t xd xclk to write data valid ? 44 ? 32 ns t xdh write data hold relative to xclk 4 ? 4 ? ns 1 t xoe xclk to oe active ? 31 ? 25 ns t xoeh oe hold relative to xclk 4 ? 4 ? ns t ds read data setup relative to xclk 13 ? 9 ? ns t dh read data hold relative to xclk 21 ? 19 ? ns 1, 3, 4 t xbw xclk to bw valid ? 35 ? 28 ns t xbwh bw hold relative to xclk 4 ? 4 ? ns t aweh address hold relative to we inactive 0 ? 0 ? ns t dweh data hold relative to we inactive 0 ? 0 ? ns t aceh address hold relative to ce inactive 0 ? 0 ? ns t dceh data hold relative to ce inactive 0 ? 0 ? ns t xras xclk to ras valid ? 26 ? 21 ns t xrash ras hold relative to xclk 2 ? 2 ? ns t xcas xclk to cas valid ? 32 ? 26 ns t xcash cas hold relative to xclk 4 ? 4 ? ns t asr dram row address setup relative to ras 10 ? 4 ? ns t asc dram column address setup relative to cas 10 ? 5 ? ns t dsc dram write data setup relative to cas 10 ? 5 ? ns 2
LH77790B 18 thermal & electrical specification programmable peripheral interface, ppi the ppi has three different modes of operation shown in figure 9 through figure 13. modes 1 and 2 assign alias names to port c when used as control signals depending on the mode of operation. table 11 shows a cross reference between the alias names which are used in the ac timing diagrams for modes 1 and 2 and the 790b external i/o names. figure 9. programmable peripheral interface (mode 0, output) ac timing arm2-108 t xa t xah t xpo xclk a25 - a0 pwe * ppi port (a, b, or c) internal ppi address reflected on 790b external address bus valid data out from 790 note: * = 790b internal signals shown for reference (790b internal peripheral write enable)
LH77790B thermal & electrical specification 19 figure 10. programmable peripheral interface (mode 0, input) ac timing arm2-109 note: * = 790b internal signals shown for reference (790b internal peripheral output enable) t xa t xah internal ppi address reflected on 790b external address bus valid data in from peripheral port input sampled t p0ih t p0is xclk a25 - a0 poe * ppi port (a, b, or c)
LH77790B 20 thermal & electrical specification figure 11. programmable peripheral interface (mode 1, input) ac timing arm2-110 t xa t stb t stib t stin t pih t pis t xint1 t xah valid data in from peripheral 790 reads captured data internal ppi address reflected on 790b external bus notes: 1. * = internal signal shown for reference (790b internal peripheral output enable) 2. ** = asynchronous signals xclk a25 - a0 poe * stb ** ibf ** intr ** ppi port (a or b) t xibf
LH77790B thermal & electrical specification 21 figure 12. programmable peripheral interface (mode 1, output) ac timing arm2-111 notes: 1. * = 790b internal signal shown for reference (790 internal peripheral write enable) 2. ** = asynchronous signals t xah t xobf t xint2 t xpo t acin t acob t ack xclk a25 - a0 pwe * ack ** intr ** ppi port (a or b) obf ** internal ppi address reflected on 790b external address bus valid data out from 790b
LH77790B 22 thermal & electrical specification figure 13. programmable peripheral interface (mode 2, bi-directional) ac timing arm2-112 t xah t xa t xobf t stib t stb t pih t pis t acd t acdh t xibf notes: 1. * = 790b internal signals shown for reference 2. ** = asynchronous signals t stin t acob t ack t xnt2 xclk a 25 - a 0 pwe * ack ** intr ** ppi port (a only) obf ** ibf ** stb ** poe * internal ppi address reflected on 790b external address bus valid data in from peripheral valid data out from 790b internal ppi address reflected on 790b external address bus
LH77790B thermal & electrical specification 23 table 11. ppi cross reference alias mode 1 (input) mode 1 (output) mode 2 (bi-directional) port a port b port a port b port a stb pc4 pc2 ?? pc4 ibf pc5 pc1 ?? pc5 intr pc3 pc0 pc3 pc0 pc3 obf ?? pc7 pc1 pc7 ack ?? pc6 pc2 pc6 table 12. ppi ac specification parameter description 3.3 v range 5.0 v range unit min. max. min. max. t xpo xclk to data out valid ? 54 ? 41 ns t p0is port input setup relative to xclk (mode 0) 40 ? 41 ? ns t stib stb to ibf ? 34 ? 27 ns t pis port input setup relative to stb (modes 1 & 2) 12 ? 12 ? ns t p0ih port input hold relative to xclk (mode 0) 10 ? 7 ? ns t pih port input hold relative to stb (modes 1 & 2) 10 ? 7 ? ns t stin stb to intr ? 32 ? 25 ns t xint1 xclk to intr (mode 1 input) ? 78 ? 57 ns t xibf xclk to ibf ? 52 ? 40 ns t stb stb pulse width 17 ? 14 ? ns t xint2 (bit a) xclk to intr (mode 1 output & mode 2) ? 86 ? 56 ns t xint2 (port b) xclk to intr (mode 1 output & mode 2) ? 57 ? 44 ns t xobf xclk to obf ? 57 ? 44 ns t ack ack pulse width 15 ? 12 ? ns t acin ack to intr ? 34 ? 27 ns t acob ack to obf ? 44 ? 28 ns t acd ack to data out valid ? 39 ? 27 ns t acdh data out hold relative to ack 6 ? 6 ? ns
LH77790B 24 thermal & electrical specification external reset figure 14. LH77790B external reset ac timing table 13. external reset ac specifications parameter description (3.3 v range) (5.0 v range) unit min. typ. max. min. typ. max. t rstiw reseti pulse width (once sampled low) 8.5 ?? 8.5 ?? xclk t rstov reseto valid (once reseti sampled low) ? 3.5 ?? 3.5 ? xclk t rstoh reseto hold (once reseti sampled high) ? 1 ?? 1 ? xclk arm2-120 t rstiw t rstov xclk reseti * reseto note: * = reseti is an asynchronous input, it is sampled on the rising edge of xclk clock. t rstoh 11 10 9 8 7 6 5 4 3 1 2
LH77790B thermal & electrical specification 25 lcd controller the lcd controller signals (vd[7:0], cp1, cp2, s, mclk, lcdcntl) are fully program- mable to drive most common passive lcd panels. the ? basic timing ? section of chapter 10 in the LH77790B user guide, best describes the relationship between the output sig- nals and the control registers in the lcd controller. the following tables and equations are repeated here for convenience. note: decimal ? equivalent ? values, as defined in the corresponding parameters tables, must be used in timing equations. the following equations (see above note) and parameters describe the relationship between lcd input clock, s, cp1, cp2, and mclk. t lcdclk = clkdiv t lcd_in_clk (t lcd_in_clk = xclk period) t s = t cp1 duty t cp1 = t pxfr + t cp1w + t 12 t pxfr , t cp1w , and t cp2 vary from one display mode to another. their typical values are shown in table 15. table 14. lcd controller parameter description parameter description note duty number of cp1 pulses per frame (lcd_duty) 1 bc number of memory bytes in a horizontal line (lcd_bc) 1 cp1w line pulse high width (lcd_cp1w) 1 clkdiv clock frequency divider (lcd_clkdiv) 1 t lcd_in_clk lcd input clock from power management unit t lcdclk lcd reference clock (output of clock divider) t s frame pulse period t cp1 line pulse period t cp2 shift clock period t pxfr pixels transfer time per line t cp1w line pulse high width time t 12 current frame cp1 to current frame cp2 t 12f current frame cp1 to next frame cp2 t 21 cp2 to cp1 t ds data setup time t dh data hold time t ss s signal setup time t sh s signal hold time t 1m cp1 to mclk inverting
LH77790B 26 thermal & electrical specification other timing parameters are shown in table 16. notes: 1. since this delay happens once a frame, its effect on the frame rate is small, t 12 will be used in the timing equations. 2. mclk clock changes on a falling edge of cp1 clock as programmed by lcd_mclkw register. 3. actual timing may vary from those calculated depending on current instruction executed, memory speed, dram refresh rate, etc. table 15. typical ac timing for lcd controller (3.3 v and 5.5 v ranges) display mode t pxfr t cp1w t cp2 1a (4-bit) 2 bc t cp 2 (cp1w+1/2) t cp 2 2 t lcdclk 1b (8-bit) bc t cp 2 (cp1w+1/2) t cp 2 4 t lcdclk 2bc t cp 2 (cp1w+1/2) t cp 2 4 t lcdclk 3a (4-bit) 2 bc t cp 2 (cp1w-1/2) t cp 2 4 t lcdclk 3b (8-bit) bc t cp 2 (cp1w) t cp 2 8 t lcdclk 4bc t cp 2 (cp1w+1/2) t cp 2 8 t lcdclk 52 bc t cp 2 (cp1w-1/2) t cp 2 4 t lcdclk 6bc t cp 2 (cp1w+1/2) t cp 2 8 t lcdclk table 16. other typical lcd timing parameters (3.3 v and 5.5 v ranges) variable value notes t ds 1/2 t cp1 t dh 1/2 t cp1 t 12 1/2 t cp1 t 12f variable 1 t 21 1/2 t cp1 t sh 3.5 t cp1 t ss t pxfr + t cp1w ? t sh t 1m 02
LH77790B thermal & electrical specification 27 figure 15. lcd controller ac timing vd[7:0] data last row t ds t dh t pxfr t 12f t cp1w t cp1 t s t 21 t ss t sh t cp2 data data data data data invalid data cp2 cp1 s mclk vd[7:0] cp1 s mclk invalid data new frame new frame row 1 row 2 last row row 1 invalid data invalid data invalid data invalid data invalid data arm2-86 row 1 t 12 t 1m
LH77790B 28 thermal & electrical specification package specifications figure 16. LH77790B 176-pin tqfp (thin quad flat pack) pin assignment 120 121 122 123 124 125 126 127 128 129 130 131 132 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 xclk nc nc a0 a1 vcc vss a6 a7 a10 a12 a15 a17 a19 vss a21 a23 32 33 vss 144 143 vss vcc pa2 pa1 ctclk ctout2 ctgate2 ctgate1 vss reseto ctgate0 uclk rxd2 txd0 vss rxd1 rxd0 reseti vss vcc ctout1 ctout0 vcc int0 int1 int2 int3 int4 int5 pwm2 160 159 158 157 156 155 154 153 152 151 150 149 148 173 172 175 176 174 171 170 169 168 167 166 165 164 163 162 161 147 146 145 142 141 140 139 138 137 136 135 134 133 vcc test3 test2 bb test1 test0 tdi vss vcc tms tck pc7 pc6 pc4 vcc pc2/dtr0 pb7/dsr0 pb6/dcd0 pb5/ri0 pb3/cts1 vss vcc xclkdis pc5 pc0/rts1 pc1/rts0 pb2/ri1 vss nc nc d5 d4 nc nc d6 d9 d7 vcc ras0 ce0/cas0 ce1/cas1 ce2/cas2 ce3/cas3 ce4/cas4 ce5/cas5 vss vcc we oe bw wait vss vd0 vd1 vd2 vd3 vd4 vd5 vd6 vd7 vcc top view tdo 77790-3 34 35 36 37 38 39 40 d0 d1 pwm1 pwm0 lcdcntl s mclk cp1 cp2 pb1 pb0 pa7 pa6 pa5 pa4 pa3 56 57 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 77 76 78 79 80 81 82 83 84 85 86 87 88 75 vcc vss vss a2 a3 a4 a5 a8 a9 a11 vcc a16 a18 vcc a20 a22 a24 a25 d2 d3 vcc vss d8 vss d10 d11 d12 d13 d14 d15 pa0 txd1 txd2 adbe pc3 vss pb4/cts0 a14 a13 176-pin tqfp ras1 LH77790B embedded microcontroller nc nc nc nc nc nc nc nc nc nc
LH77790B thermal & electrical specification 29 figure 17. LH77790B package specification 176tqfp 176tqfp (tqfp-176-p-2424) 24.20 23.80 1.00 ref. 1.00 ref. 0.50 typ. 0.28 0.12 0.65 0.35 0.20 0.00 26.30 25.70 24.20 23.80 26.30 25.70 25.2 24.8 dimensions in mm detail 1.70 max. 0.175 0.075 0.10
north america europe asia sharp microelectronics of the americas 5700 nw pacific rim blvd. camas, wa 98607, u.s.a. phone: (360) 834-2500 facsimile: (360) 834-8903 http://www.sharpsma.com sharp electronics (europe) gmbh microelectronics division sonninstra?e 3 20097 hamburg, germany phone: (49) 40 2376-2286 facsimile: (49) 40 2376-2232 http://www.sharpmed.com sharp corporation integrated circuits group 2613-1 ichinomoto-cho tenri-city, nara, 632, japan phone: (07436) 5-1321 facsimile: (07436) 5-1532 http://www.sharp.co.jp ?

▲Up To Search▲

Price & Availability of LH77790B

	To Download LH77790B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .